Design And Implementation Of An ADC/DAC-Free Walsh-Hadamard Transform Based Neural Network Accelerator Using Bit-Plane Processing

Abstract

Energy-efficient neural-network inference on edge platforms is limited by multiplication-intensive computation, frequent memory access, and the converter overhead of analog compute-in-memory architectures. This paper presents an ADC/DAC-free neural accelerator based on the Walsh-Hadamard Transform (WHT) and bit-plane processing. The proposed architecture replaces conventional multiply-accumulate operations with addition and subtraction by exploiting the binary ±1 coefficients of the Hadamard matrix. Multibit inputs are decomposed into bit planes and processed from the most significant bit to the least significant bit, enabling precision-scalable computation using a compact datapath. A comparator-based decision stage removes the need for high-resolution analog-to-digital conversion, while digital bit accumulation reconstructs the final output. Soft-thresholding is incorporated to create transform-domain sparsity, and an early-termination controller avoids the processing of insignificant lower bit planes. The complete architecture consists of an input buffer, bit-plane extractor, block WHT compute core, comparator, weighted accumulator, threshold unit, and control logic suitable for Verilog realization. The proposed design offers a multiplier-free, converter-free, regular, and scalable solution for low-power edge intelligence.