Thermal-Aware Modeling of Physical Unclonable Functions for Reliable Hardware Security in 3D Integrated Circuits

Abstract

Three-dimensional integrated circuits (3D ICs) are intended to achieve high integration density and short vertical interconnections, however, with the stacking of active layers, power density, thermal gradient, and reliability sensitivity increase. Physical unclonable functions (PUFs) are appealing choices for hardware-security primitives, as they rely on manufacturing variations that are not controllable to produce a device-specific response. The delays and device variations of the process, however, are also temperature sensitive, which is the source of the PUF entropy. In this paper, a thermal-aware modeling framework for PUFs embedded in 3D ICs based on TSV is developed. It integrates a vertically stacked thermal model with a temperature dependent PUF response model, allowing local temperature, vertical position, TSV proximity and process variations to be simultaneously taken into account for reliability evaluation. Ring-oscillators and Arbiter-type PUFs are considered representative structures and the variation caused by TSV is considered as an extra entropy source. The evaluation method is based on the main evaluation metrics: reliability, uniqueness, uniformity, bit-error rate, intra-chip Hamming distance, and thermal sensitivity. Existing 3D-IC PUF research shows that process variation from CMOS, TSV, can both introduce entropy, and recent reliability studies demonstrate that temperature and voltage variation can have a significant impact on PUF stability. The proposed framework is a systematic approach to the thermal-aware placement of PUFs, modelling of their responses, and optimization for reliability in a stacked hardware-security architecture.